The 64-bit resolution allows more accurate modeling of MEMS sensors and actuators and the software is designed to operate in parallel with Matlab and Virtuoso design software from Mathworks and Cadence Design Systems Inc., respectively.
The extension to 64-bits has been accompanied by an option to tune the software between accuracy and speed. Reduced-order models can be exported in Verilog-A format, for use by IC designers. These exported models simulate 100X faster than fully non-linear MEMS+ models and are compatible with all commercial analog/mixed-signal circuit simulators that support the industry-standard Verilog-A hardware description language.
Within Coventor's range of software MEMS+ 4.0 sits alongside CoventorWare and SEMulator3D. The combination provides support for the design of accelerometers, gyroscopes, microphones and many other types of MEMS.
"We were able to create a Verilog-A ROM [reduced order model] of a complex gyro design in just a few minutes, allowing our ASIC team to work in parallel with the MEMS team on further design iterations," said Tero Sillanpaa, ASIC design manager at Murata Electronics Oy, in a statement issued by Coventor. "Harmonic simulations in Cadence showed that the model maintained the expected modal frequencies and was stable. Moreover, transient startup simulations were very fast, on the order of 25 seconds CPU time for one seconds real time, before front-end electronic components including RC parasitics were added."
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